%FILENAME%
vtr-9.0.0-1-aarch64.pkg.tar.xz

%NAME%
vtr

%BASE%
vtr

%VERSION%
9.0.0-1

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
7429736

%ISIZE%
28679348

%MD5SUM%
e1b2da62aa0e01ddb4c6448167c89ce2

%SHA256SUM%
20b0a7e7f619c101b8710225cc6f6ebd5755ce86113f4f0edbf2b036fd9b889c

%PGPSIG%
iQIzBAABCAAdFiEEaLNTfzmjE7PldNBndxk/FSvb5qYFAmhOLeoACgkQdxk/FSvb5qYT2w//ZTx/PBEw6Oi6jy6KCcRIbNoWJyziMz1LXQqJQYfbuObi5DZ/YZpNqmzEd7bHUGebnv8tzwl4zRp4XFQ8l+31IC6oi0lFopMqWiEsX7N6j0edjq2xV6KdHJ50XGSC/ItPoAcpJ2zwthqnJy27AxuJLTKv2tPMFHE6O659kKgXLUY68sUr7e3ZGLwCPmQ6F84k2fYYN5/jATLyaPI9BpGQ8u2zux7yOJJIexV6YbHR8OLStJrnrooBrsEWaniyBAtuUgjBQJy/crNZhomM6QekfboLQDC7HcwAoXlm7FvjGcvZKLXIMGcXq4bVUwJ2RcjU69ippuWLS0TlUEJrs0zlNPSe6XqTPXXBlJ+lol3zkflp1jNb+/jObhf4wSC9yTkXOlcCA3+bPU7bB2I0agwnAsyd1FdK9AOvfhCY078ihAxUqlrjf+uSNYE8yGSi32u0XX1vh7mcW/QyXGwXOdufbFpV6NoToKpL69EWbuQBxw/R+ePJMUk+eCR6NT9/lz0E2zcW96G4dePsLQVWf+fSDFYJFfVXcEERc9LsjpXyjdyqZFEmCUlbUzusS++825OILD6g/i0Fw5ziYxqACA57wJC9pbikyTREo/lfb/aS2EwQOlFpzTF7c2ygPbVrgI/zuxqKNNJuCIV3IwGWcohxBBq4h8rar3ZXIfn6dQ57nLs=

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
aarch64

%BUILDDATE%
1749953208

%PACKAGER%
Arch Linux ARM Build System <builder+seattle@archlinuxarm.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake
wget

